# set IOSTANDARD LVCMOS15 [get_ports {led_pins[0]}]
# set IOSTANDARD LVCMOS15 [get_ports {led_pins[1]}]
# set IOSTANDARD LVCMOS15 [get_ports {led_pins[2]}]
# set IOSTANDARD LVCMOS15 [get_ports {led_pins[3]}]
# set DRIVE 12 [get_ports {led_pins[0]}]
# set DRIVE 12 [get_ports {led_pins[1]}]
# set DRIVE 12 [get_ports {led_pins[2]}]
# set DRIVE 12 [get_ports {led_pins[3]}]
# set SLEW SLOW [get_ports {led_pins[0]}]
# set SLEW SLOW [get_ports {led_pins[1]}]
# set SLEW SLOW [get_ports {led_pins[2]}]
# set SLEW SLOW [get_ports {led_pins[3]}]
# set IOSTANDARD LVCMOS25 [get_ports {led_pins[4]}]
# set IOSTANDARD LVCMOS25 [get_ports {led_pins[5]}]
# set IOSTANDARD LVCMOS25 [get_ports {led_pins[6]}]
# set IOSTANDARD LVCMOS25 [get_ports {led_pins[7]}]
# set DRIVE 12 [get_ports {led_pins[4]}]
# set DRIVE 12 [get_ports {led_pins[5]}]
# set DRIVE 12 [get_ports {led_pins[6]}]
# set DRIVE 12 [get_ports {led_pins[7]}]
# set SLEW SLOW [get_ports {led_pins[4]}]
# set SLEW SLOW [get_ports {led_pins[5]}]
# set SLEW SLOW [get_ports {led_pins[6]}]
# set SLEW SLOW [get_ports {led_pins[7]}]
# set IOSTANDARD LVDS [get_ports clk_pin_p]
# set IOSTANDARD LVCMOS25 [get_ports dac_clr_n_pin]
# set IOSTANDARD LVCMOS25 [get_ports dac_cs_n_pin]
# set IOSTANDARD LVCMOS25 [get_ports lb_sel_pin]
# set IOSTANDARD LVCMOS15 [get_ports rst_pin]
# set IOSTANDARD LVCMOS25 [get_ports rxd_pin]
# set IOSTANDARD LVCMOS25 [get_ports spi_clk_pin]
# set IOSTANDARD LVCMOS25 [get_ports spi_mosi_pin]
# set IOSTANDARD LVCMOS25 [get_ports txd_pin]

# set PACKAGE_PIN E17 [get_ports rxd_pin]
# set PACKAGE_PIN F23 [get_ports rst_pin]
# set LOC OLOGIC_X0Y101 [get_cells {samp_gen_i0/led_o_reg[7]}]
# set LOC OLOGIC_X0Y103 [get_cells {samp_gen_i0/led_o_reg[5]}]
# set LOC OLOGIC_X0Y104 [get_cells {samp_gen_i0/led_o_reg[6]}]
# set LOC OLOGIC_X0Y106 [get_cells {samp_gen_i0/led_o_reg[4]}]
# set LOC OLOGIC_X0Y117 [get_cells lb_ctl_i0/txd_o_reg]
# set LOC OLOGIC_X0Y118 [get_cells dac_spi_i0/spi_mosi_o_reg]
# set LOC OLOGIC_X0Y130 [get_cells dac_spi_i0/dac_cs_n_o_reg]
# set LOC OLOGIC_X0Y134 [get_cells dac_spi_i0/dac_clr_n_o_reg]
# set LOC OLOGIC_X0Y59 [get_cells {samp_gen_i0/led_o_reg[0]}]
# set LOC OLOGIC_X0Y61 [get_cells {samp_gen_i0/led_o_reg[2]}]
# set LOC OLOGIC_X0Y62 [get_cells {samp_gen_i0/led_o_reg[1]}]
# set LOC OLOGIC_X0Y64 [get_cells {samp_gen_i0/led_o_reg[3]}]
# set PACKAGE_PIN G15 [get_ports dac_clr_n_pin]
# set PACKAGE_PIN E15 [get_ports dac_cs_n_pin]
# set PACKAGE_PIN H24 [get_ports {led_pins[0]}]
# set PACKAGE_PIN H21 [get_ports {led_pins[1]}]
# set PACKAGE_PIN G21 [get_ports {led_pins[2]}]
# set PACKAGE_PIN J26 [get_ports {led_pins[3]}]
# set PACKAGE_PIN K16 [get_ports {led_pins[4]}]
# set PACKAGE_PIN L18 [get_ports {led_pins[5]}]
# set PACKAGE_PIN M17 [get_ports {led_pins[6]}]
# set PACKAGE_PIN K18 [get_ports {led_pins[7]}]
# set PACKAGE_PIN G19 [get_ports spi_mosi_pin]
# set PACKAGE_PIN F20 [get_ports txd_pin]
# set PACKAGE_PIN AA3 [get_ports clk_pin_p]
# set PACKAGE_PIN AA2 [get_ports clk_pin_n]
# set PACKAGE_PIN C17 [get_ports lb_sel_pin]
# set PACKAGE_PIN G17 [get_ports spi_clk_pin]


# set IOB TRUE [all_fanin -only_cells -startpoints_only -flat [all_outputs]]

